12055 search results - page 215 / 2411 » High Performance Banking |
137
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ISCA
2008
IEEE
15 years 11 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
197
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ICDE
2012
IEEE
13 years 7 months ago
2012
IEEE
— Accurate query performance prediction (QPP) is central to effective resource management, query optimization and query scheduling. Analytical cost models, used in current genera...
126
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ISCA
2007
IEEE
15 years 11 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
126
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ISCA
2000
IEEE
15 years 9 months ago
2000
IEEE
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
117
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CII
2007
15 years 5 months ago
2007
Nowadays companies have to face the rapid evolution of their competitive environment. In the field of design, project managers are aware of both the impact of the designers’ com...