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SAC
2008
ACM
14 years 9 months ago
A self-balancing striping scheme for NAND-flash storage systems
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load eac...
Yu-Bin Chang, Li-Pin Chang
SAC
2008
ACM
14 years 9 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
IJHPCA
2007
165views more  IJHPCA 2007»
14 years 9 months ago
High Performance Development for High End Computing With Python Language Wrapper (PLW)
This paper presents a design and implementation of a system that leverages interactive scripting environment to the needs of scientific computing. The system allows seamless tran...
Piotr Luszczek, Jack Dongarra
PADS
1996
ACM
15 years 1 months ago
Design of High Level Modelling / High Performance Simulation Environments
Advances in massively parallel platforms are increasing the prospects for high performance discrete event simulation. Still the di culty in parallel programming persists and there...
Bernard P. Zeigler, Doohwan Kim
93
Voted
CISSE
2008
Springer
14 years 11 months ago
Using B-trees to Implement Water: a Portable, High Performance, High-Level Language
- To achieve high performance, the next generation of high-level programming languages should incorporate databases as core technology. Presented here are the design considerations...
Aubrey Jaffer, Mike Plusch, Robert Nilsson