Sciweavers

12055 search results - page 41 / 2411
» High Performance Banking
Sort
View
IEEEARES
2009
IEEE
14 years 7 months ago
Reducing the Cost of Session Key Establishment
Scenarios such as online banking, mobile payment systems, stock trading, selling merchandise, and a host of other applications that need a high level of security have moved from th...
Bezawada Bruhadeshwar, Kishore Kothapalli, Maddi S...
IPPS
2006
IEEE
15 years 3 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
15 years 1 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
HPCA
2002
IEEE
15 years 10 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
15 years 2 months ago
Reducing register ports for higher speed and lower energy
The key issues for register file design in high-performance processors are access time and energy. While previous work has focused on reducing the number of registers, we propose...
Il Park, Michael D. Powell, T. N. Vijaykumar