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DAC
2001
ACM
16 years 4 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
HSNMC
2004
Springer
106views Multimedia» more  HSNMC 2004»
15 years 8 months ago
Performance Evaluation of a Probabilistic Packet Filter Optimization Algorithm for High-Speed Network Monitoring
Because of the ever-increasing popularity of the Internet, network monitoring becomes very mission critical to guarantee the operation of IP networks, e.g. to detect network failur...
Jan Coppens, Stijn De Smet, Steven Van den Berghe,...
MSS
1999
IEEE
150views Hardware» more  MSS 1999»
15 years 7 months ago
Performance Benchmark Results for Automated Tape Library High Retrieval Rate Applications - Digital Check Image Retrievals
Benchmark tests have been designed and conducted for the purpose of evaluating the use of automated tape libraries in on-line digital check image retrieval applications. This type...
John Gniewek, George Davidson, Bowen Caldwell
WWW
2009
ACM
16 years 3 months ago
Highly scalable web applications with zero-copy data transfer
The performance of server-side applications is becoming increasingly important as more applications exploit the Web application model. Extensive work has been done to improve the ...
Toyotaro Suzumura, Michiaki Tatsubori, Scott Trent...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 8 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin