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APCSAC
2001
IEEE
15 years 7 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
FPL
2000
Springer
116views Hardware» more  FPL 2000»
15 years 7 months ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...
146
Voted
BMCBI
2004
97views more  BMCBI 2004»
15 years 3 months ago
Performance of a genetic algorithm for mass spectrometry proteomics
Background: Recently, mass spectrometry data have been mined using a genetic algorithm to produce discriminatory models that distinguish healthy individuals from those with cancer...
Neal O. Jeffries
PARA
2004
Springer
15 years 9 months ago
HPC-ICTM: The Interval Categorizer Tessellation-Based Model for High Performance Computing
Abstract. This paper presents the Interval Categorizer Tessellationbased Model (ICTM) for the simultaneous categorization of geographic regions considering several characteristics ...
Marilton S. de Aguiar, Graçaliz Pereira Dim...
150
Voted
ISCAS
2002
IEEE
190views Hardware» more  ISCAS 2002»
15 years 8 months ago
A high performance JPEG2000 architecture
—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of ...
Kishore Andra, Chaitali Chakrabarti, Tinku Acharya