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GLOBECOM
2006
IEEE
15 years 3 months ago
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
Rongsen He, José G. Delgado-Frias
SPAA
1996
ACM
15 years 1 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
SLIP
2003
ACM
15 years 2 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
INFOCOM
2003
IEEE
15 years 2 months ago
Exploiting Parallelism to Boost Data-Path Rate in High-Speed IP/MPLS Networking
Abstract—Link bundling is a way to increase routing scalability whenever a pair of Label Switching Routers in MPLS are connected by multiple parallel links. However, link bundlin...
Indra Widjaja, Anwar Elwalid
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 3 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...