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DAC
2011
ACM
13 years 9 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
SECON
2008
IEEE
15 years 3 months ago
A Multi-AP Architecture for High-Density WLANs: Protocol Design and Experimental Evaluation
—Fast proliferation of IEEE 802.11 wireless devices has led to the emergence of High-Density (HD) Wireless Local Area Networks (WLANs), where it is challenging to improve the thr...
Yanfeng Zhu, Zhisheng Niu, Qian Zhang, Bo Tan, Zhi...
ANCS
2011
ACM
13 years 9 months ago
A Scalability Study of Enterprise Network Architectures
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
Brent Stephens, Alan L. Cox, Scott Rixner, T. S. E...
IPPS
2006
IEEE
15 years 3 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
FCCM
2004
IEEE
133views VLSI» more  FCCM 2004»
15 years 1 months ago
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area,...
Zachary K. Baker, Viktor K. Prasanna