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96
Voted
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
15 years 4 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
ISVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
HPCA
2008
IEEE
15 years 9 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
ECUMN
2004
Springer
15 years 1 months ago
2004
Springer
The integration of wireless LANs (WLANs) and 3G systems performed at core network level requires very little modifications to the current 3GPP architecture and provides a large set...