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AINA
2007
IEEE
15 years 11 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...
146
Voted
TELETRAFFIC
2007
Springer
15 years 11 months ago
Modeling and Predicting End-to-End Response Times in Multi-tier Internet Applications
Many Internet applications employ multi-tier software architectures. The performance of such multi-tier Internet applications is typically measured by the end-toend response times...
Sandjai Bhulai, Swaminathan Sivasubramanian, Rober...
134
Voted
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 11 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
111
Voted
DSN
2005
IEEE
15 years 10 months ago
Probabilistic QoS Guarantees for Supercomputing Systems
Supercomputing systems must be able to reliably and efficiently complete their assigned workloads, even in the presence of failures. This paper proposes a system that allows the ...
Adam J. Oliner, Larry Rudolph, Ramendra K. Sahoo, ...
SIGCOMM
2009
ACM
15 years 11 months ago
VL2: a scalable and flexible data center network
To be agile and cost effective, data centers should allow dynamic resource allocation across large server pools. In particular, the data center network should enable any server to...
Albert G. Greenberg, James R. Hamilton, Navendu Ja...