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» High Performance Routing in a LEO Satellite Network
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DATE
2003
IEEE
99views Hardware» more  DATE 2003»
15 years 5 months ago
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch...
Erland Nilsson, Mikael Millberg, Johnny Öberg...
IJSNET
2011
55views more  IJSNET 2011»
14 years 3 months ago
Testing network protocols and signal attenuation in packed food transports
: Two sensor network protocols for the monitoring of packed food products were tested in different sea containers. The packet rate and the signal strength of all sensor-to-sensor l...
Reiner Jedermann, Markus Becker, Carmelita Gö...
FPL
2008
Springer
153views Hardware» more  FPL 2008»
15 years 1 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
PCRCW
1997
Springer
15 years 4 months ago
ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing
In recent years, theChaos Project at theUniversityofWashingtonhas analyzed and simulated a dozen routing algorithms. Three new routing algorithms have been invented; of these, the...
Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Law...
SLIP
2004
ACM
15 years 5 months ago
Interconnect-power dissipation in a microprocessor
Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the...
Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum ...