307 search results - page 25 / 62 » High Performance X Servers in the Kdrive Architecture |
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
ISCA
2010
IEEE
14 years 8 months ago
2010
IEEE
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
AAECC
2007
Springer
14 years 9 months ago
2007
Springer
Abstract. We present new performance models and a new, more compact data structure for cache blocking when applied to the sparse matrixvector multiply (SpM×V) operation, y ← y +...
ICDCS
2000
IEEE
15 years 2 months ago
2000
IEEE
In light of advances in processor and networking technology, especially the emergenceof networkattached disks,the traditional clientserver architecture of file systems has become...
MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...