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HOTI
2005
IEEE
15 years 3 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
GRID
2007
Springer
15 years 3 months ago
Integrating multi-level molecular simulations across heterogeneous resources
— Biomolecular simulations play a key role in the study of complex biological processes at microscopic levels in which macromolecules such as proteins are involved. The simulatio...
Yudong Sun, Steve McKeever, Kia Balali-Mood, Mark ...
80
Voted
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 4 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
IEEEPACT
2009
IEEE
14 years 7 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...
CODES
2009
IEEE
15 years 4 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...