154 search results - page 16 / 31 » High level cache simulation for heterogeneous multiprocessor... |
173
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ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
3DIC
2009
IEEE
15 years 2 months ago
2009
IEEE
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
148
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ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way. A two-p...
MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
CODES
2007
IEEE
15 years 4 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...