154 search results - page 17 / 31 » High level cache simulation for heterogeneous multiprocessor... |
81
Voted
CF
2004
ACM
15 years 3 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
MOBIQUITOUS
2005
IEEE
15 years 3 months ago
2005
IEEE
Caching techniques can be used to reduce bandwidth consumption and data access delay in wireless ad hoc networks. When cache is used, cache consistency issues must be addressed. T...
EUROMICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
CMOS technology should, over the next few years, reach lithography of under 0.1¡ . This provides a die area improvement of a factor of 10 over today’s technology. What is the b...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a ...
LCTRTS
2004
Springer
15 years 3 months ago
2004
Springer
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...