154 search results - page 20 / 31 » High level cache simulation for heterogeneous multiprocessor... |
98
Voted
HPCA
2005
IEEE
15 years 5 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
108
Voted
HIPC
2003
Springer
15 years 4 months ago
2003
Springer
1 Since I/O-intensive tasks running on a heterogeneous cluster need a highly effective usage of global I/O resources, previous CPUor memory-centric load balancing schemes suffer ...
114
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EUROPAR
2010
Springer
14 years 12 months ago
2010
Springer
Today, it is possible to associate multiple CPUs and multiple GPUs in a single shared memory architecture. Using these resources efficiently in a seamless way is a challenging issu...
102
Voted
CSB
2003
IEEE
15 years 5 months ago
2003
IEEE
Physical map reconstruction in the presence of errors is a central problem in genetics of high computational complexity. A parallel genetic algorithm for a maximum likelihood esti...
112
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CODES
2009
IEEE
15 years 3 months ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...