154 search results - page 21 / 31 » High level cache simulation for heterogeneous multiprocessor... |
118
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WSC
1997
15 years 1 months ago
1997
Distributed discrete event simulation techniques aim at an acceleration of the execution of a self-contained simulation model by the spatial decomposition of that model and the co...
ISCA
1994
IEEE
15 years 3 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
TCAD
2008
14 years 11 months ago
2008
The verification of a system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, ...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
108
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MICRO
2003
IEEE
15 years 4 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...