154 search results - page 7 / 31 » High level cache simulation for heterogeneous multiprocessor... |
ANSS
2004
IEEE
15 years 1 months ago
2004
IEEE
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
124
click to vote
HIPEAC
2011
Springer
13 years 9 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
75
Voted
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
Real-time streaming signal processing systems typically desire high throughput and low latency. Many such systems can be modeled as synchronous data flow graphs. In this paper, w...
FCCM
2006
IEEE
15 years 3 months ago
2006
IEEE
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...