154 search results - page 8 / 31 » High level cache simulation for heterogeneous multiprocessor... |
ANCS
2009
ACM
14 years 7 months ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
ISSS
2002
IEEE
15 years 2 months ago
2002
IEEE
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For ...
CIDR
2007
14 years 11 months ago
2007
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...