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ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
15 years 9 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
118
Voted
SSDBM
2010
IEEE
153views Database» more  SSDBM 2010»
15 years 8 months ago
Scalable Clustering Algorithm for N-Body Simulations in a Shared-Nothing Cluster
Abstract. Scientists’ ability to generate and collect massive-scale datasets is increasing. As a result, constraints in data analysis capability rather than limitations in the av...
YongChul Kwon, Dylan Nunley, Jeffrey P. Gardner, M...
135
Voted
PLDI
2010
ACM
15 years 8 months ago
Supporting speculative parallelization in the presence of dynamic data structures
The availability of multicore processors has led to significant interest in compiler techniques for speculative parallelization of sequential programs. Isolation of speculative s...
Chen Tian, Min Feng, Rajiv Gupta
130
Voted
DATE
2002
IEEE
124views Hardware» more  DATE 2002»
15 years 8 months ago
Crosstalk Alleviation for Dynamic PLAs
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
146
Voted
IEEEINTERACT
2002
IEEE
15 years 8 months ago
Code Cache Management Schemes for Dynamic Optimizers
A dynamic optimizer is a software-based system that performs code modifications at runtime, and several such systems have been proposed over the past several years. These systems ...
Kim M. Hazelwood, Michael D. Smith
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