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HPCA
2006
IEEE
16 years 5 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
FPL
1995
Springer
137views Hardware» more  FPL 1995»
15 years 8 months ago
High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform
General purpose custom computing platforms, such as Splash-2, have demonstrated the ability to enter mainstream computing not only due to their near application-specific speeds bu...
Ramana V. Rachakonda, Peter M. Athanas, A. Lynn Ab...
128
Voted
APPINF
2003
15 years 6 months ago
Hardware Impact on Communication Performance of Beowulf LINUX Cluster
There exist a lot of models of parallel computation, amongst which LogP and LogGP are famous and suitable to describe the framework of communication process of Beowulf LINUX Clust...
Yuan Tang, Yun-Quan Zhang, Jia-Chang Sun, Yu-Cheng...
ICDCS
2009
IEEE
15 years 2 months ago
The Case for Spam-Aware High Performance Mail Server Architecture
The email volume per mailbox has largely remained low and unchanged in the past several decades, and hence mail server performance has largely remained a secondary issue. The stee...
Abhinav Pathak, Syed Ali Raza Jafri, Y. Charlie Hu
DSD
2006
IEEE
95views Hardware» more  DSD 2006»
15 years 8 months ago
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
Zhonghai Lu, Ingo Sander, Axel Jantsch