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191
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 5 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
DAGSTUHL
2008
15 years 6 months ago
Improving the Performance of a Verified Linear System Solver Using Optimized Libraries and Parallel Computation
Abstract. A parallel version of the self-verified method for solving linear systems was presented in [19, 18]. In this research we propose improvements aiming at a better performan...
Mariana Luderitz Kolberg, Gerd Bohlender, Dalcidio...
WIMOB
2007
IEEE
15 years 11 months ago
On the Performance of Hybrid Wireless/Wired Mesh Networks
Sebastian Max, Lothar Stibor, Guido R. Hiertz, Dee...
ICEIS
2000
IEEE
15 years 9 months ago
Architectural Considerations with Distributed Computing
We understand distributed systems as a collection of distributed computation resources that work together as one harmonious system. It is the great achievement of computer network...
Yibing Wang, Robert M. Hyatt, Barrett R. Bryant
151
Voted
ARITH
2001
IEEE
15 years 8 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee