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TPDS
2002
105views more  TPDS 2002»
15 years 4 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
GLOBECOM
2008
IEEE
15 years 5 months ago
Highly Memory-Efficient LogLog Hash for Deep Packet Inspection
As the network line rates reach 40 Gbps today and 100 Gbps in the near future, performing deep packet inspection (DPI) in the Network Intrusion Detection and Prevention Systems (NI...
Masanori Bando, N. Sertac Artan, H. Jonathan Chao
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
15 years 11 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
CCGRID
2008
IEEE
15 years 11 months ago
Experiences with Fine-Grained Distributed Supercomputing on a 10G Testbed
This paper shows how lightpath-based networks can allow challenging, fine-grained parallel supercomputing applications to be run on a grid, using parallel retrograde analysis on ...
Kees Verstoep, Jason Maassen, Henri E. Bal, John W...
GLOBECOM
2007
IEEE
15 years 11 months ago
Performance Analysis of V-BLAST with Optimum Power Allocation
—Comprehensive performance analysis of the unordered V-BLAST algorithm with various power allocation strategies is presented, which makes use of analytical tools and resorts to M...
Victoria Kostina, Sergey Loyka