6138 search results - page 114 / 1228 » High performance computing through parallel processing |
155
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ISCC
2006
IEEE
15 years 10 months ago
2006
IEEE
In this paper, we present a Dynamic Load Balancing (DLB) policy for problems characterized by a highly irregular search tree, whereby no reliable workload prediction is available....
147
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GRAPHICSINTERFACE
2000
15 years 5 months ago
2000
We introduce an algorithm for high-quality, interactive light field rendering from only a small number of input images with dense depth information. The algorithm bridges the gap ...
154
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CJ
2006
15 years 4 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
129
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SC
1993
ACM
15 years 8 months ago
1993
ACM
The High Performance Storage System (HPSS) is a mature Hierarchical Storage Management (HSM) system that was developed around a network-centered architecture, with client access t...
124
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ATS
2009
IEEE
15 years 11 months ago
2009
IEEE
Embedded memory quality is critical to overall chip quality. New defect mechanisms that occur at advanced process nodes (65nm and below) are often more pronounced in memories due ...