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» High performance computing through parallel processing
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ICPADS
2008
IEEE
15 years 10 months ago
Quarc: A Novel Network-On-Chip Architecture
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC [16]. The Quarc scheme significantly outperforms the Spidergon NoC through balancing t...
Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi
125
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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 9 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
122
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WOTUG
2007
15 years 4 months ago
A Process Oriented Approach to USB Driver Development
Abstract. Operating-systems are the core software component of many modern computer systems, ranging from small specialised embedded systems through to large distributed operating-...
Carl G. Ritson, Fred R. M. Barnes
114
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GCC
2003
Springer
15 years 9 months ago
Computing Pool: A Simplified and Practical Computational Grid Model
Even though grid research is prosperous in an extensive context, few grid platforms for high performance computing are practical and in operation so far. Since most applications a...
Peng Liu, Yao Shi, Sanli Li
138
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BMCBI
2005
246views more  BMCBI 2005»
15 years 3 months ago
ParPEST: a pipeline for EST data analysis based on parallel computing
Background: Expressed Sequence Tags (ESTs) are short and error-prone DNA sequences generated from the 5' and 3' ends of randomly selected cDNA clones. They provide an im...
Nunzio D'Agostino, Mario Aversano, Maria Luisa Chi...