While previous CPU- or memory-centric load balancing schemes are capable of achieving the effective usage of global CPU and memory resources in a cluster system, the cluster exhib...
Xiao Qin, Hong Jiang, Yifeng Zhu, David R. Swanson
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Many researchers have been focusing on the outcomes and consequences of the rapid increase and proliferation of mobile wireless technologies. If it is not already the case, it wil...
Lara B. Deek, Kevin C. Almeroth, Mike P. Wittie, K...