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CODES
2004
IEEE
15 years 10 months ago
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
We present a analytical framework to identify the tradeoffs and performance impacts associated with different SoC platform configurations in the specific context of implementing m...
Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakra...
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 12 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
CLUSTER
2002
IEEE
15 years 11 months ago
I/O Analysis and Optimization for an AMR Cosmology Application
In this paper, we investigate the data access patterns and file I/O behaviors of a production cosmology application that uses the adaptive mesh refinement (AMR) technique for it...
Jianwei Li, Wei-keng Liao, Alok N. Choudhary, Vale...
FPGA
2010
ACM
294views FPGA» more  FPGA 2010»
15 years 11 months ago
Axel: a heterogeneous cluster with FPGAs and GPUs
This paper describes a heterogeneous computer cluster called Axel. Axel contains a collection of nodes; each node can include multiple types of accelerators such as FPGAs (Field P...
Kuen Hung Tsoi, Wayne Luk
ASPDAC
2006
ACM
118views Hardware» more  ASPDAC 2006»
16 years 11 days ago
A probabilistic analysis of pipelined global interconnect under process variations
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
Navneeth Kankani, Vineet Agarwal, Janet Meiling Wa...