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DAC
2009
ACM
16 years 1 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
181
Voted
HOTI
2005
IEEE
16 years 23 days ago
Performance Characterization of a 10-Gigabit Ethernet TOE
Though traditional Ethernet based network architectures such as Gigabit Ethernet have suffered from a huge performance difference as compared to other high performance networks (e...
Wu-chun Feng, Pavan Balaji, C. Baron, Laxmi N. Bhu...
SIGOPS
2008
123views more  SIGOPS 2008»
15 years 7 months ago
Comparative evaluation of overlap strategies with study of I/O overlap in MPI-IO
Many scientific applications use parallel I/O to meet the low latency and high bandwidth I/O requirement. Among many available parallel I/O operations, collective I/O is one of th...
Christina M. Patrick, Seung Woo Son, Mahmut T. Kan...
GRID
2006
Springer
15 years 7 months ago
Overhead Analysis of Grid Workflow Applications
In this paper we propose a systematic approach to performance analysis of workflow applications on the Grid. We introduce an ideal model for the workflow execution time and explain...
Francesco Nerieri, Radu Prodan, Thomas Fahringer, ...
DCOSS
2009
Springer
16 years 1 months ago
Online Coding for Reliable Data Transfer in Lossy Wireless Sensor Networks
Bulk transport underlies data exfiltration and code update facilities in WSNs, but existing approaches are not designed for highly lossy and variable-quality links. We observe tha...
Anthony D. Wood, John A. Stankovic