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ICS
2003
Tsinghua U.
16 years 13 days ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
SC
1992
ACM
15 years 11 months ago
Optimal Tracing and Replay for Debugging Message-Passing Parallel Programs
A common debugging strategy involves reexecuting a program (on a given input) over and over, each time gaining more information about bugs. Such techniques can fail on message-pas...
Robert H. B. Netzer, Barton P. Miller
TOG
2012
271views Communications» more  TOG 2012»
13 years 9 months ago
Mass splitting for jitter-free parallel rigid body simulation
We present a parallel iterative rigid body solver that avoids common artifacts at low iteration counts. In large or real-time simulations, iteration is often terminated before con...
Richard Tonge, Feodor Benevolenski, Andrey Voroshi...
HPDC
2009
IEEE
16 years 2 months ago
Maintaining reference graphs of globally accessible objects in fully decentralized distributed systems
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
Björn Saballus, Thomas Fuhrmann
IPPS
2005
IEEE
16 years 25 days ago
COTS Clusters vs. the Earth Simulator: An Application Study Using IMPACT-3D
In 2002, Japan announced the Earth Simulator—a supercomputer based on low-volume vector processors and a custom network—and reported that computational scientists had used it ...
Daniel G. Chavarría-Miranda, Guohua Jin, Jo...