Sciweavers

6138 search results - page 591 / 1228
» High performance computing through parallel processing
Sort
View
ICS
2000
Tsinghua U.
15 years 11 months ago
Push vs. pull: data movement for linked data structures
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetchin...
Chia-Lin Yang, Alvin R. Lebeck
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
CCGRID
2008
IEEE
16 years 1 months ago
On the Optimization of Resource Utilization in Distributed Multimedia Applications
—The application and research area of Multimedia Content Analysis (MMCA) considers all aspects of the automated extraction of new knowledge from large multimedia data streams and...
R. Yang, Robert D. van der Mei, D. Roubos, Frank J...
CF
2006
ACM
16 years 1 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
CORR
2010
Springer
159views Education» more  CORR 2010»
15 years 7 months ago
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
Bin Wu, Guido Masera