733 search results - page 112 / 147 » High performance in tree-based parallel architectures |
JPDC
2007
14 years 11 months ago
2007
Object space (OS) parallelization of an efficient direct volume rendering algorithm for unstructured grids on distributed-memory architectures is investigated. The adaptive OS de...
105
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EUROPAR
2009
Springer
15 years 3 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
SASP
2008
IEEE
15 years 6 months ago
2008
IEEE
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
100
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ICS
2004
Tsinghua U.
15 years 5 months ago
2004
Tsinghua U.
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
102
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HPDC
2009
IEEE
15 years 6 months ago
2009
IEEE
This paper explores the feasibility of a cost-efficient storage architecture that offers the reliability and access performance characteristics of a high-end system. This architec...