Sciweavers

733 search results - page 40 / 147
» High performance in tree-based parallel architectures
Sort
View
IPPS
1999
IEEE
15 years 4 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas
CAP
2010
14 years 6 months ago
Parallel arithmetic encryption for high-bandwidth communications on multicore/GPGPU platforms
In this work we study the feasibility of high-bandwidth, secure communications on generic machines equipped with the latest CPUs and General-Purpose Graphical Processing Units (GP...
Ludovic Jacquin, Vincent Roca, Jean-Louis Roch, Mo...
SC
2005
ACM
15 years 5 months ago
Transparent, Incremental Checkpointing at Kernel Level: a Foundation for Fault Tolerance for Parallel Computers
We describe the software architecture, technical features, and performance of TICK (Transparent Incremental Checkpointer at Kernel level), a system-level checkpointer implemented ...
Roberto Gioiosa, José Carlos Sancho, Song J...
IPPS
1998
IEEE
15 years 3 months ago
Airshed Pollution Modeling: A Case Study in Application Development in an HPF Environment
In this paper, we describe our experience with developing Airshed, a large pollution modeling application, in the Fx programming environment. We demonstrate that high level parall...
Jaspal Subhlok, Peter Steenkiste, James M. Stichno...
NPC
2010
Springer
14 years 10 months ago
Exposing Tunable Parameters in Multi-threaded Numerical Code
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
Apan Qasem, Jichi Guo, Faizur Rahman, Qing Yi