733 search results - page 74 / 147 » High performance in tree-based parallel architectures |
124
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IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
WWW
2010
ACM
15 years 6 months ago
2010
ACM
The web browser is a CPU-intensive program. Especially on mobile devices, webpages load too slowly, expending significant time in processing a document’s appearance. Due to powe...
IJPP
2006
14 years 11 months ago
2006
Abstract. In order to address the problems faced in the wireless communications domain, picoChip has devised the picoArrayTM . The picoArrayTM is a tiled-processor architecture, co...
SIGADA
2001
Springer
15 years 4 months ago
2001
Springer
The last years have seen an increasing, albeit restricted simulation of large-scale networks on shared memory parallel platforms. As the complexity of communication protocols and ...
103
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IEEEPACT
2000
IEEE
15 years 4 months ago
2000
IEEE
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...