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CCS
2011
ACM
13 years 9 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
IEAAIE
2010
Springer
14 years 7 months ago
Constructive Neural Networks to Predict Breast Cancer Outcome by Using Gene Expression Profiles
Abstract. Gene expression profiling strategies have attracted considerable interest from biologist due to the potential for high throughput analysis of hundreds of thousands of gen...
Daniel Urda, José Luis Subirats, Leonardo F...
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 1 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
80
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ICOIN
2001
Springer
15 years 1 months ago
A Study of Flow-Based Traffic Admission Control Algorithm in the ATM-Based MPLS Network
This paper presents the Differentiated Services (DiffServ) over ATM based Multiprotocol Label Switching (MPLS) core network architecture. This network supports the Integrated Serv...
Gyu Myoung Lee, Jun Kyun Choi
HPCA
2009
IEEE
15 years 10 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...