116 search results - page 4 / 24 » High throughput architecture for packet classification using... |
FPL
2006
Springer
15 years 1 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
JUCS
2007
14 years 9 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
110
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ASPDAC
2011
ACM
14 years 1 months ago
2011
ACM
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
103
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FPL
2003
Springer
15 years 2 months ago
2003
Springer
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
FCCM
2006
IEEE
15 years 3 months ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...