116 search results - page 6 / 24 » High throughput architecture for packet classification using... |
INFOCOM
2005
IEEE
15 years 3 months ago
2005
IEEE
Packet Classification (PC) has been a critical data path function for many emerging networking applications. An interesting approach is the use of TCAM to achieve deterministic, hi...
FCCM
2008
IEEE
15 years 3 months ago
2008
IEEE
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
TVLSI
2010
14 years 4 months ago
2010
:- This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as...