8 search results - page 2 / 2 » High-Level Allocation to Minimize Internal Hardware Wastage |
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
STORAGESS
2005
ACM
13 years 11 months ago
2005
ACM
Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently acces...