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138
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MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
15 years 5 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve
107
Voted
DAC
2010
ACM
15 years 4 months ago
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
Lin Huang, Qiang Xu
108
Voted
CASES
2006
ACM
15 years 6 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
IFIPTCS
2000
15 years 4 months ago
Masaccio: A Formal Model for Embedded Components
Masaccio is a formal model for hybrid dynamical systems which are built from atomic discrete components (di erence equations) and atomic continuous components (di erential equation...
Thomas A. Henzinger
116
Voted
HIPC
2009
Springer
14 years 10 months ago
Continuous performance monitoring for large-scale parallel applications
Traditional performance analysis techniques are performed after a parallel program has completed. In this paper, we describe an online method for continuously monitoring the perfor...
Isaac Dooley, Chee Wai Lee, Laxmikant V. Kal&eacut...