Sciweavers

1024 search results - page 145 / 205
» High-Level Execution Time Analysis
Sort
View
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 6 months ago
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
With power dissipation becoming an increasingly vexing problem across many classes of computer systems, measuring power dissipation of real, running systems has become crucial for...
Canturk Isci, Margaret Martonosi
94
Voted
SAC
2010
ACM
15 years 5 months ago
An algorithm to generate the context-sensitive synchronized control flow graph
The verification of industrial systems specified with CSP often implies the analysis of many concurrent and synchronized components. The cost associated to these analyses is usu...
Marisa Llorens, Javier Oliver, Josep Silva, Salvad...
107
Voted
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
15 years 5 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
89
Voted
SAC
1996
ACM
15 years 4 months ago
An enabling optimization for C++ virtual functions
Gaining the code re-use advantages of object oriented programming requires dynamic function binding, which allows a new subclass to override a function of a superclass. Dynamic bi...
Bradley M. Kuhn, David Binkley
EXPCS
2007
15 years 4 months ago
Empirical performance assessment using soft-core processors on reconfigurable hardware
Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretica...
Richard Hough, Praveen Krishnamurthy, Roger D. Cha...