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103
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CJ
2006
84views more  CJ 2006»
14 years 11 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
83
Voted
GW
2005
Springer
141views Biometrics» more  GW 2005»
15 years 5 months ago
From Acoustic Cues to an Expressive Agent
This work proposes a new way for providing feedback to expressivity in music performance. Starting from studies on the expressivity of music performance we developed a system in wh...
Maurizio Mancini, Roberto Bresin, Catherine Pelach...
EMSOFT
2003
Springer
15 years 4 months ago
Intelligent Editor for Writing Worst-Case-Execution-Time-Oriented Programs
Abstract. To guarantee timeliness in hard real-time systems the knowledge of the worst-case execution time (WCET) for its time-critical tasks is mandatory. Accurate and correct WCE...
Janosch Fauster, Raimund Kirner, Peter P. Puschner
JUCS
2006
141views more  JUCS 2006»
14 years 11 months ago
Constraint Based Methods for Biological Sequence Analysis
: The need for processing biological information is rapidly growing, owing to the masses of new information in digital form being produced at this time. Old methodologies for proce...
Maryam Bavarian, Verónica Dahl
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
14 years 9 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...