1024 search results - page 92 / 205 » High-Level Execution Time Analysis |
130
click to vote
RTSS
2006
IEEE
15 years 6 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
129
Voted
IPPS
1999
IEEE
15 years 5 months ago
1999
IEEE
Parallelizing compiler technology has improved in recent years. One area in which compilers have made progress is in handling DOACROSS loops, where crossprocessor data dependencie...
99
Voted
ERSA
2006
15 years 2 months ago
2006
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
100
click to vote
CSUR
1999
15 years 14 days ago
1999
useful for optimizing compilers [15], partial evaluators [11], abstract debuggers [1], models-checkers [2], formal verifiers [13], etc. The difficulty of the task comes from the fa...
96
Voted
WCET
2008
15 years 2 months ago
2008
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...