74 search results - page 10 / 15 » High-Level Modelling, Analysis, and Verification on FPGA-Bas... |
DAC
2008
ACM
16 years 18 days ago
2008
ACM
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
CAV
2006
Springer
15 years 3 months ago
2006
Springer
Example Guided Abstraction Refinement (CEGAR) [6] framework. A number of wellengineered software model-checkers are available, e.g., SLAM [1] and BLAST [12]. Why build another one?...
81
Voted
DAC
2007
ACM
16 years 18 days ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
114
Voted
ECBS
2003
IEEE
15 years 4 months ago
2003
IEEE
Heterogeneous embedded systems, where configurable or application specific hardware devices (FPGAs and ASICs) are used alongside traditional processors, are becoming more and more...
109
Voted
DAC
2003
ACM
16 years 17 days ago
2003
ACM
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...