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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
15 years 3 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
88
Voted
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
14 years 7 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar
CODES
2007
IEEE
15 years 3 months ago
ESL design and HW/SW co-verification of high-end software defined radio platforms
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
A. C. H. Ng, J. W. Weijers, Miguel Glassee, Thomas...
EUROMICRO
2007
IEEE
15 years 3 months ago
Partial Verification of Software Components: Heuristics for Environment Construction
Code model checking of software components suffers from the well-known problem of state explosion when applied to highly parallel components, despite the fact that a single compon...
Pavel Parizek, Frantisek Plasil
ASPDAC
2008
ACM
200views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Non-Gaussian statistical timing analysis using second-order polynomial fitting
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Lerong Cheng, Jinjun Xiong, Lei He