74 search results - page 5 / 15 » High-Level Modelling, Analysis, and Verification on FPGA-Bas... |
FAC
2000
14 years 9 months ago
2000
Formal approaches to the design of interactive systems rely on reasoning about properties of the t a very high level of abstraction. Specifications to support such an approach typi...
ACSW
2006
14 years 10 months ago
2006
Formal specification and verification of protocols have been credited for uncovering protocol flaws; revealing inadequacies in protocol design of the Initial Stage and Negotiation...
106
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ATVA
2008
Springer
14 years 11 months ago
2008
Springer
UPPAAL PORT is a new tool for component-based design and analysis of embedded systems. It operates on the hierarchically structured continuous time component modeling language Save...
VSTTE
2005
Springer
15 years 2 months ago
2005
Springer
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...
82
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CAV
2007
Springer
15 years 1 months ago
2007
Springer
In automatic software verification, we have observed a theoretical convergence of model checking and program analysis. In practice, however, model checkers are still mostly concern...