74 search results - page 6 / 15 » High-Level Modelling, Analysis, and Verification on FPGA-Bas... |
EURODAC
1995
IEEE
15 years 29 days ago
1995
IEEE
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
ECBS
2007
IEEE
15 years 1 months ago
2007
IEEE
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
ACSD
2001
IEEE
15 years 1 months ago
2001
IEEE
One of the corner stones of formal methods is the notion traction enables analysis. By the construction of act model we can trade implementation detail for analytical power. The i...
71
Voted
ECBS
2006
IEEE
15 years 1 months ago
2006
IEEE
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...