74 search results - page 9 / 15 » High-Level Modelling, Analysis, and Verification on FPGA-Bas... |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling c...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...
68
Voted
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
80
Voted
CAV
2009
Springer
15 years 10 months ago
2009
Springer
Recent development on distributed systems has shown that a variety of fairness constraints (some of which are only recently defined) play vital roles in designing self-stabilizing ...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...