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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 3 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
JSA
2007
142views more  JSA 2007»
15 years 1 months ago
Efficient FPGA hardware development: A multi-language approach
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
15 years 10 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
GLOBECOM
2009
IEEE
15 years 8 months ago
Development Framework for Implementing FPGA-Based Cognitive Network Nodes
—This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture ware abstraction, an adaptive run-time system for managing co...
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris...
MIDDLEWARE
2007
Springer
15 years 7 months ago
Rule-based reasoning about qualitative spatiotemporal relations
This paper is about a novel rule-based approach for reasoning about qualitative spatiotemporal relations among technology-rich autonomous objects, to which we refer to as artifact...
Clemens Holzmann