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» High-Level Power Modeling, Estimation, and Optimization
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EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 1 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
CASES
2007
ACM
15 years 1 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
ICCAD
2003
IEEE
120views Hardware» more  ICCAD 2003»
15 years 6 months ago
RTL Power Optimization with Gate-Level Accuracy
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
Qi Wang, Sumit Roy
ECCV
1994
Springer
15 years 1 months ago
Markov Random Field Models in Computer Vision
A variety of computer vision problems can be optimally posed as Bayesian labeling in which the solution of a problem is dened as the maximum a posteriori (MAP) probability estimate...
Stan Z. Li
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
15 years 1 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona