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» High-Level State Machine Specification and Synthesis
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ICCTA
2007
IEEE
13 years 10 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
FPL
1999
Springer
147views Hardware» more  FPL 1999»
13 years 10 months ago
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
FORTE
2008
13 years 7 months ago
Detecting Communication Protocol Security Flaws by Formal Fuzz Testing and Machine Learning
Network-based fuzz testing has become an effective mechanism to ensure the security and reliability of communication protocol systems. However, fuzz testing is still conducted in a...
Guoqiang Shu, Yating Hsu, David Lee
RE
2004
Springer
13 years 11 months ago
Modeling and Composing Scenario-Based Requirements with Aspects
There has been significant recent interest, within the Aspect-Oriented Software Development (AOSD) community, in representing crosscutting concerns at various stages of the softwa...
João Araújo, Jon Whittle, Dae-Kyoo K...
ICCAD
1994
IEEE
76views Hardware» more  ICCAD 1994»
13 years 10 months ago
An efficient procedure for the synthesis of fast self-testable controller structures
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
Sybille Hellebrand, Hans-Joachim Wunderlich