64 search results - page 4 / 13 » High-Performance Extendable Instruction Set Computing |
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SAMOS
2010
Springer
14 years 8 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
EUROPAR
1999
Springer
15 years 1 months ago
1999
Springer
Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism ILP techniques that are traditionally used in high perform...
CCS
2007
ACM
15 years 3 months ago
2007
ACM
sion of an extended abstract published in Proceedings of ACM CCS 2007, ACM Press, 2007. We present new techniques that allow a return-into-libc attack to be mounted on x86 executa...
MICRO
1991
IEEE
15 years 1 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...