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ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
15 years 3 months ago
Fast bit permutation unit for media enhanced microprocessors
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-...
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, ...
ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
15 years 2 months ago
High-speed processor for quantum-computing emulation and its applications
A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this pr...
Minoru Fujishima, Kaoru Saito, M. Onouchi, Koichir...
ISVLSI
2003
IEEE
138views VLSI» more  ISVLSI 2003»
15 years 2 months ago
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
Sarah E. Frost, Arun Rodrigues, Charles A. Giefer,...
IFIP
1999
Springer
15 years 1 months ago
Design Error Diagnosis in Digital Circuits without Error Model
We describe a new method for design error diagnosis in digital circuits, that doesn’t use any error model. A diagnostic specific pre-analysis of the circuit extracts a subcircui...
Raimund Ubar, Dominique Borrione
COMCOM
2010
150views more  COMCOM 2010»
14 years 9 months ago
Convergence of trajectories and optimal buffer sizing for MIMD congestion control
We study the interaction between the MIMD (Multiplicative Increase Multiplicative Decrease) congestion control and a bottleneck router with Drop Tail buffer. We consider the probl...
Yi Zhang, Alexei B. Piunovskiy, Urtzi Ayesta, Kons...